Cisc vs Risc

CISC (Complex Instruction Set Computers)
The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible.
One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware.
Examples of CISC processors are the System/360 (excluding the ‘scientific’ Model 44), VAX, PDP-11, Motorola 68000 family, and Intel x86 architecture based processors.


Characteristics of a CISC architecture:
* Emphasis on hardware;
* Includes multi-clock complex instructions;
* Small code sizes;
* Complex data types in hardware; some CISCs have byte string instructions, or support complex numbers;

RISC (Reduced instruction set computer) is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set ofinstructions often found in other types of architectures.
RISC processors only use simple instructions that can be executed within one clock cycle.
Well known RISC families include Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture (including PowerPC), SuperH, and SPARC.

Characteristics of a RISC architecture:
* Emphasis on software;
* Single-clock, reduced instruction only;
* Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding;
* Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design;
* Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations;
* Typically larger code sizes;
* Few data types in hardware;

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.


Author: Ali MEZGANI

My name is MEZGANI Ali. I was born back in 1978 in Rabat Morocco. My interests are Debian Linux , programming , science and music.

3 thoughts on “Cisc vs Risc”

    1. Yes, i did not describe it here.
      Well i don’t know many things about it before that you send me your feedback, In the fact, i see that EPIC is a new technology created by Intel as combination of both CISC and RISC,
      and EPIC can do many instruction executions in parallel to one another.

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